Patent · US Active

Addressable test circuit and test method for key parameters of transistors

US9817058B2 · kind B2 · utility

0Cited by
2References
19Claims
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Assignee

Inventors

Key dates

Filing dateNov 14, 2016
Grant dateNov 14, 2017
Priority date—
Expiry dateNov 14, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/0002
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

An addressable test circuit is configured to test parameters of a plurality of transistors. The addressable test circuit includes combination logic circuits including a plurality of gate circuits and are configured to select a device under test, a plurality of PADs, a plurality of address bus and data bus; wherein six or more of the data buses are test signal lines. A test method can employ the above address test circuit for testing parameters of a plurality of transistors, where the subthreshold leakage current Ioff and saturation current Idsat are measured in different signal lines respectively to ensure the accurate measurement of the two parameters in one circuit.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.