Low latency computer system power reduction
US9817465B2 · kind B2 · utility
1Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2014 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Mar 27, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Technology for handling overcurrent conditions on electrical circuits that power multiple computing modules is disclosed. Aspects of the technology include a power system adapted to provide notifications of overcurrent conditions, and computing modules adapted to reduce an operating speed thereof in response to notification of an overcurrent condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.