Management of peak power consumed by multiple memory devices
US9817595B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Feb 29, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that include multiple memory blocks. The processor is configured to hold information regarding power consumption of the memory blocks, to group at least some of the memory blocks into one or more storage groups, based on the information, such that the memory blocks in each storage group jointly consume less than a predefined power limit when the memory blocks in the storage group are applied a storage operation in parallel, and to apply the storage operation, in parallel, to the memory blocks in a selected storage group.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.