Hybrid memory systems for autonomous non-volatile memory save and restore operations
US9817610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2015 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Apr 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/313
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus forms a memory system that is physically populated into a host. In a powered-on state, the apparatus logically connects to the host through a host memory controller configured to receive host-initiated commands. The memory system includes a command buffer coupled to the host memory controller to receive the host-initiated commands. The memory system comprises both volatile memory (e.g., RAM) and non-volatile memory (e.g., FLASH). A non-volatile memory controller (NVC) is coupled to the volatile memory, and is also coupled to the non-volatile memory. A command sequence processor that is co-resident with the NVC responds to a trigger signal by logically disconnecting from the host, then dispatching command sequences that perform successive read/write operations between the volatile memory and the non-volatile memory. The successive read/write operations are performed even when the host is in a powered-down state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.