Ingress data placement
US9817786B1 · kind B1 · utility
6Cited by
3References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Oct 27, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2272
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Server computers often include one or more input/output (I/O) adapter devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O adapter device. For example, host memory descriptors can be stored in a content addressable memory unit of the I/O adapter device to facilitate placement of requested data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.