On-chip upscaling and downscaling in a camera architecture
US9818169B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2017 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | May 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N23/843
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An image capture accelerator performs accelerated processing of image data. In one embodiment, the image capture accelerator includes accelerator circuitry including a pre-processing engine and a compression engine. The pre-processing engine is configured to perform accelerated processing on received image data, and the compression engine is configured to compress processed image data received from the pre-processing engine. In one embodiment, the image capture accelerator further includes a demultiplexer configured to receive image data captured by an image sensor array implemented within, for example, an image sensor chip. The demultiplexer may output the received image data to an image signal processor when the image data is captured by the image sensor array in a standard capture mode, and may output the received image data to the accelerator circuitry when the image data is captured by the image sensor array in an accelerated capture mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.