Patent · US Active

Negative bitline write assist circuit and method for operating the same

US9818460B2 · kind B2 · utility

3Cited by

16References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Pramod Kolar · Cary, US
John R. Riley · Spicewood, US
Gunjan H. Pandya · Portland, US

Key dates

Filing date	May 23, 2016
Grant date	Nov 14, 2017
Priority date	—
Expiry date	May 23, 2036

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A negative bitline write assist circuit includes a bias capacitor configured to facilitate driving the capacitance of a bitline. The negative bitline write assist circuit may be modularly replicated within a circuit to change the amount of negative voltage on the bitline during write operations. The bitline write assist circuit may be coupled directly to the bitline, removing the need to add a pull-down transistor to the write driver.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.