Nonvolatle memory device and memory system having the same, and related memory management, erase and programming methods
US9818485B2 · kind B2 · utility
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18References
19Claims
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Key dates
| Filing date | Jun 9, 2016 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jun 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An erase method of a nonvolatile memory device includes setting an erase mode, and performing one of a normal erase operation and a quick erase operation according to the set erase mode. The normal erase operation is performed to set a threshold voltage of a memory cell to an erase state which is lower than a first erase verification level. The quick erase operation is performed to set a threshold voltage of a memory cell to a pseudo erase state which is lower than a second erase verification level. The second erase verification level is higher than the first erase verification level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.