Stacked memory chip having reduced input-output load, memory module and memory system including the same
US9818707B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2015 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1434
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked memory chip includes a chip input-output pad unit, a first semiconductor die and a second semiconductor die. The chip input-output pad unit includes a chip command-address pad unit, a lower chip data pad unit and an upper chip data pad unit that are to be connected to an external device. The first semiconductor die electrically is connected to the chip command-address pad unit and the lower chip data pad unit and electrically disconnected from the upper chip data pad unit. The second semiconductor die electrically is connected to the chip command-address pad unit and the upper chip data pad unit and electrically disconnected from the lower chip data pad unit. The input-output load may be reduced by selectively connecting each of the stacked semiconductor dies to one of the lower chip data pad unit and the upper chip data pad unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.