Arrangement of passivation layers in a pixel unit of an array substrate and display device
US9818762B2 · kind B2 · utility
1Cited by
5References
18Claims
0Family size
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Inventor
Key dates
| Filing date | Dec 10, 2013 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jan 17, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array substrate and a display device are disclosed. The array substrate includes: a TFT, a pixel electrode layer driven by the TFT, a data line, a first passivation layer and a common electrode layer disposed on a substrate, the data line is for driving the TFT, the first passivation layer is disposed between the pixel electrode layer and the common electrode layer, the array substrate further includes a second passivation layer disposed between the common electrode layer and the data line and located in a region corresponding to the data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.