Multi-channel transmitter synchronization circuitry
US9819478B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2012 |
| Grant date | Nov 14, 2017 |
| Priority date | — |
| Expiry date | Jul 27, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an integrated circuit has one or more multi-channel transmitters, each transmitter having synchronization circuitry that synchronizes different copies of a reset signal used to reset different sets of TX channel circuitry used to generate the multiple TX signals, to reduce the skew between the different TX signals. Each set of synchronization circuitry has (at least) two synchronization stages that re-time different copies of the reset signal to a selected clock signal. In one implementation, the integrated circuit has (at least) two quads, each of which can generate four different TX signals, where both quads can be configured to use the same clock signal to re-time different copies of the reset signal such that the eight different TX signals are all synchronized to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.