Patent · US Active

Built-in self test system, system on a chip and method for controlling built-in self tests

US9823296B2 · kind B2 · utility

9Cited by

4References

16Claims

0Family size

Assignee

NXP USA, Inc. · US

Inventors

Manfred Thanner · Neubiberg, DE
Carl Culshaw · Wigan, GB
Juergen Frank · Kirchberg, DE
Michael Andreas Staudenmaier · Munich, DE

Key dates

Filing date	Jun 7, 2012
Grant date	Nov 21, 2017
Priority date	—
Expiry date	Jun 9, 2033

Classification

Technology area (CPC G)Physics
CPC primaryG01R31/31721
WIPO fieldMeasurement
WIPO sectorInstruments

Abstract

A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.