Average clock adjustment for data acquisition system and method
US9823368B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Dec 15, 2015 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Dec 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01V2200/12
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system and method for adjusting a clock signal of a seismic data acquisition system. The system includes a data acquisition device having an oscillator that generates a clock signal; a clock adjustment module that receives a time reference signal and the clock signal and outputs an adjusted clock signal; and an analog-to-digital convertor configured to transform analog data into digital data having a sampling rate (FDATA). A sampling frequency (fADC) of the analog-to-digital convertor is selected to be at least twice the sampling rate (FDATA).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.