Patterned poly silicon structure as top electric contact to MOS-type optical modulators
US9823499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Oct 27, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2202/105
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A metal-oxide-semiconductor (MOS) type semiconductor device, comprising a silicon substrate, a first cathode electrode and a second cathode electrode coupled to the silicon substrate and located on distal ends of the silicon substrate, a poly-silicon (Poly-Si) gate proximally located above the silicon substrate and between the first cathode electrode and the second cathode electrode, wherein the Poly-Si gate comprises a first post extending orthogonally relative to the silicon substrate comprising a first doped silicon slab, a second post extending orthogonally relative to the silicon substrate comprising a second doped silicon slab, wherein the second post is positioned so as to create a width between the first post and the second post, an anode electrode coupled to the first post and the second post and extending laterally from the first post to the second post, and a dielectric layer disposed between the first silicon substrate and the second silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.