Register file circuit design process

US9824171B2 · kind B2 · utility

Assignee

• Apple Inc. · US

Inventors

• Harsha Krishnamurthy · San Jose, US
• Mridul Agarwal · Sunnyvale, US
• Shyam Balasubramanian · Santa Clara, US
• Christopher Scott Thomas · Horseheads, US
• Rajat Goel · Saratoga, US
• Rohit Kumar · Bengaluru, IN
• Muthukumaravelu Velayoudame · Fremont, US

Key dates

• Filing date: Aug 6, 2015
• Grant date: Nov 21, 2017
• Expiry date: Mar 17, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/39
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.