Asynchronous pulse domain processor with adaptive circuit and reconfigurable routing
US9824311B1 · kind B1 · utility
177Cited by
15References
21Claims
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Key dates
| Filing date | Apr 23, 2014 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Aug 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/09
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A liquid state machine pulse domain neural processor circuit comprising an asynchronous input filter circuit provided for, at any given time, receiving a series of analog input signals and generating in response a set of time-encoded values that depend on the series of analog input signals received at said given time and before said given time; and an asynchronous trainable readout map circuit for transforming at least a portion of said set of time encoded values into output signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.