Dynamic subroutine linkage optimizing shader performance
US9824484B2 · kind B2 · utility
3Cited by
16References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 12, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2200/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Allocation of memory registers for shaders by a processor is described herein. For each shader, registers are allocated based on the shader's level of complexity. Simpler shader instances are restricted to a smaller number of memory registers. More complex shader instances are allotted more registers. To do so, developers' high level shading level (HLSL) language includes template classes of shaders that can later be replaced by complex or simple versions of the shader. The HLSL is converted to bytecode that can be used to rasterize pixels on a computing device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.