DRAM access in self-refresh state
US9824742B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and method are directed to accessing a Dynamic Random Access Memory (DRAM) system. A DRAM controller is designed to determine that a DRAM bank of a DRAM system is in a self-refresh state and allow one or more commands to access the DRAM bank without exiting the self-refresh state. The DRAM controller may select these one or more commands, based on one or more of a clock frequency, traffic conditions related to requests for accessing the DRAM bank, or a command type. The one or more commands may include at least one of read (RD), write (WR), or precharge (PRE) commands received while the DRAM bank is in the self-refresh state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.