Fusible link cell with dual bit storage
US9824769B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | May 4, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/165
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fuse-programmable register or memory location having a plurality of fusible links of differing electrical characteristics in parallel. In one embodiment, three fusible links with different resistances are provided, such that application of a programming voltage non-uniformly distributes the current among the links, allowing varying voltages to selectively blow one or more of the links. Sensing of the programmed state is performed by applying a voltage across the parallel links and measuring the current in comparison with a plurality of reference currents. Reduction in the overhead chip area per bit and in the serial data communication latency are obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.