Patent · US Active

ESD clamp circuit

US9825022B2 · kind B2 · utility

4Cited by
6References
14Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 1, 2015
Grant dateNov 21, 2017
Priority date
Expiry dateJun 24, 2035

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D89/911

Abstract

An ESD clamp circuit includes a power supply, a ground supply, an ESD detection transistor, a capacitor having a first terminal connected to the power supply and a second terminal connected to a gate of the ESD detection transistor, and a first resistor connected in series with the capacitor between the power and ground supplies. The ESD clamp circuit also includes a clamp transistor having a first terminal connected to the power supply and a second terminal connected to the ground terminal, an inverter having an input connected to a first terminal of the ESD detection transistor and an output connected to the gate of the clamp transistor, a feedback transistor connected across the inverter, and a second resistor having a first terminal connected to the gate of the clamp transistor and to a second terminal to the ground supply.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.