Array substrate manufacturing method
US9825069B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Oct 14, 2014 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Oct 14, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D99/00
Abstract
An array substrate manufacturing method, including: forming an active layer of a thin film transistor, in which photoresist with a partial thickness at a location corresponding to a channel area between source/drain electrodes of the thin film transistor on the active layer is reserved; forming a source/drain metal layer, and further forming source/drain electrodes; lifting off the photoresist with the partial thickness on the channel area between the source/drain electrodes. The array substrate manufacturing method can avoid damaging the metal oxide layer in the etching process for source/drain electrodes, and lower production cost, simplify processes, and increase yield and product profit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.