Electronic component package and method for manufacturing the same
US9825209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2013 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Dec 20, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H20/0365
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing an electronic component package. The method includes (i) providing a package precursor in which an electronic component is embedded such that an electrode of the electronic component is exposed at a surface of a sealing resin layer; (ii) forming a first metal plating layer such that the first metal plating layer is in contact with the exposed surface of the electrode of the electronic component; (iii) disposing a metal foil in face-to-face spaced relationship with respect to the first metal plating layer; and (iv) forming a second metal plating layer. In step (iv), the second metal plating layer is formed so as to fill a clearance between the first metal plating layer and the metal foil, thereby integrating the metal foil, the first metal plating layer and the second metal plating layer with each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.