Dynamic error vector magnitude duty cycle correction
US9825591B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Nov 21, 2017 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/7236
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.