Scheduler and CPU performance controller cooperation
US9830187B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2015 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Jun 5, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an application programming interface (API) is defined that enables a thread scheduler to communicate thread information to the CPU performance controller when dispatching a thread to a processor or processor core. When dispatching a thread, the scheduler may communicate thread information including thread state information, a general “importance” of the thread as defined by a priority level and/or quality of service (QoS) classification, a measurement of the scheduler dispatch latency for the thread, or architectural information regarding the instructions within the thread, such as whether the thread is contains 64-bit or 32-bit instructions. The performance controller can use the information provided by the scheduler to make performance control decisions for the processor cores within the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.