Replaying memory transactions while resolving memory access faults
US9830276B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2017 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Feb 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/684
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention is a parallel processing unit (PPU) that includes one or more streaming multiprocessors (SMs) and implements a replay unit per SM. Upon detecting a page fault associated with a memory transaction issued by a particular SM, the corresponding replay unit causes the SM, but not any unaffected SMs, to cease issuing new memory transactions. The replay unit then stores the faulting memory transaction and any faulting in-flight memory transaction in a replay buffer. As page faults are resolved, the replay unit replays the memory transactions in the replay buffer—removing successful memory transactions from the replay buffer—until all of the stored memory transactions have successfully executed. Advantageously, the overall performance of the PPU is improved compared to conventional PPUs that, upon detecting a page fault, stop performing memory transactions across all SMs included in the PPU until the fault is resolved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.