Data output circuit and memory device including the same
US9830960B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Oct 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device may include a data output circuit configured to multiplex a plurality of data signals read from a memory cell array, wherein the data output circuit includes a clock boosting circuit configured to receive a plurality of internal clock signals generated based on a first power voltage, and to generate a plurality of boosted clock signals by boosting the plurality of internal clock signals based on a second power voltage having a voltage level greater than that of the first power voltage, and a data output driver configured to multiplex and output the plurality of data signals synchronized with the boosted clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.