Semiconductor device having multiport memory
US9830975B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2017 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | May 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.