Semiconductor devices having expanded recess for bit line contact
US9831172B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Dec 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.