Method and device for error decision
US9831984B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2016 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | May 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0065
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of error decision, comprising: for each of a plurality of demodulated decision information in a codeword, identifying by a controller, a decoded bit for the demodulated decision as an erasable error bit if the demodulated decision information is larger than a first threshold and smaller than a second threshold; for all the identified erasable error bits, enumerating by a calculator, all possible combinations of the identified erasable error bits; for each combination of all enumerated possible combinations feeding by the calculator, each combination with all other decided decoded bits of the code word into a header correction checker; performing, by the header correction checker, header correction checking for each combination; and outputting, by a decision circuit connected to the header correction checker, a combination with a correct header correction check (HEC) result as an output sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.