Transmission of delay tolerant data
US9832132B2 · kind B2 · utility
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7References
19Claims
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Key dates
| Filing date | Jul 16, 2015 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Oct 8, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/70
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Transmission of delay tolerant data. An apparatus includes a processor configured to classify data, on the basis of its delay requirement, into delay tolerant data and into delay critical data, and to control transmission of the delay tolerant data with a transmitter in such a manner that the transmission of the delay tolerant data is timed to coincide with transmission of the delay critical data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.