Multiple bit rate video decoding
US9832476B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2015 |
| Grant date | Nov 28, 2017 |
| Priority date | — |
| Expiry date | Jan 31, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N21/44004
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In a video processing system including a video decoder, to handle frequent changes in the bit rate of an encoded bitstream, a video decoder can be configured to process a change in bit rates without reinitializing. The video decoder can be configured to reduce memory utilization. The video decoder can be configured both to process a change in bit rate without reinitializing while reducing memory utilization. In one implementation, the video processing system can include an interface between an application running on a host processor and the video decoder which allows the video decoder to communicate with the host application about the configuration of the video decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.