Method for managing a last level cache and apparatus utilizing the same
US9836396B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Nov 10, 2015 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Mar 23, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A last-level cache controller includes a system state monitor and a cache partitioning module. The system state monitor is configured to obtain a latency sensitivity factor, off-chip latency factors, and cache miss information for each of the processor cores. The cache partitioning module is configured to: obtain a first weighted latency according to the latency sensitivity factor, the off-chip latency factors and a first entry of the cache miss information that corresponds to a first cache partition configuration for each of the processor cores; obtain a first aggregated weighted latency according to the first weighted latency of each of the processor cores; determine whether a partition criterion is satisfied, where the partition criterion takes the first aggregated weighted latency into consideration; and partition the cache ways of the last-level cache using the first partition configuration when determining that the partition criterion is satisfied.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.