Patent · US Active

Method, apparatus and system for dynamically controlling an addressing mode for a cache memory

US9836400B2 · kind B2 · utility

5Cited by

2References

27Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Kebing Wang · Shanghai, CN
Zhaojuan Bian · Shanghai, CN
Wei Zhou · Tianjin, CN
Zhihong Wang · Singapore, SG

Key dates

Filing date	Oct 31, 2013
Grant date	Dec 5, 2017
Priority date	—
Expiry date	Aug 15, 2034

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an embodiment, a first portion of a cache memory is associated with a first core. This first cache memory portion is of a distributed cache memory, and may be dynamically controlled to be one of a private cache memory for the first core and a shared cache memory shared by a plurality of cores (including the first core) according to an addressing mode, which itself is dynamically controllable. Other embodiments are described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.