Scan driving circuit and driving method thereof, array substrate and display apparatus
US9837024B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2015 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Sep 24, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A scan driving circuit and a driving method thereof, an array substrate, and a display apparatus are disclosed. The scan driving circuit comprises: a first shift register (11) connected to one group of clock signals (CLKA) having a first clock cycle, and configured to output a first scanning signal (GA) progressively; a second shift register (12) connected to another group of clock signals (CLKB) having a second clock cycle, and configured to output a second scanning signal (GB) progressively; and a logic arithmetic device (13) connected to a first clock signal (CLK1) having a third clock cycle, connected to the first shift register (11) and the second shift register (12), and configured to output compensation signals (SC) of multiple rows; the compensation signal (SC) of any row has a wave shape the same as the first clock signal (CLK1) when a second scanning signal (GB) of a present row is at a first level, and has a wave shape the same as a first scanning signal (GA) of the present row when the second scanning signal (GB) of the present row is at a second level; and the third clock cycle is smaller than the second clock cycle. The scan driving circuit can be implemented by addin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.