NAND-based write driver for SRAM
US9837143B1 · kind B1 · utility
0Cited by
2References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Oct 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide systems and methods for reducing power consumption during the operation of a SRAM cell. Embodiments of the present invention reduce power consumption by determining switching activity, and based off a determination of low switching activity, gates off a core which is not written; and limits switching activity on the unaddressed core by applying the highest order bit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.