Dual gate semiconductor memory device with vertical semiconductor column
US9837155B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 17, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jun 17, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes: a semiconductor column extending vertically on a substrate and including a source region of a first conductivity type, an intrinsic region, and a drain region of a second conductivity type; a first gate electrode disposed adjacent to the drain region to cover the intrinsic region; a second gate electrode spaced apart from the first gate electrode and disposed adjacent to the source region to cover the intrinsic region; a first gate insulating layer disposed between the first gate electrode and the intrinsic region; and a second gate insulating layer disposed between the second gate electrode and the intrinsic region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.