Methods of forming patterns of a semiconductor devices
US9837273B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Jul 29, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.