Semiconductor apparatus
US9837349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Apr 6, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor apparatus includes gate electrodes and interlayer insulating layers alternately stacked on a substrate, channel regions penetrating through the gate electrodes and the interlayer insulating layers, a conductive layer extending from an uppermost layer among the interlayer insulating layers to the substrate by penetrating through the gate electrodes and the interlayer insulating layers between the channel regions, and having an uneven pattern on an outer side wall thereof, a spacer layer disposed on the outer side wall, and a barrier layer disposed on at least one side surface of the spacer layer, wherein the spacer layer and the barrier layer have different etch selectivities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.