Patent · US Active

Reducing parasitic leakages in transistor arrays

US9837450B2 · kind B2 · utility

0Cited by

0References

17Claims

0Family size

Assignee

Flexenable Limited · GB

Inventors

Stephan Riedel · Frankfurt am Main, DE
David Gammie · Tucson, US
Boon Hean Pui · Kuala Lumpur, MY

Key dates

Filing date	Oct 7, 2014
Grant date	Dec 5, 2017
Priority date	—
Expiry date	Oct 7, 2034

Classification

Technology area (CPC H)Electricity
CPC primaryH10K19/10
WIPO fieldAudio-visual technology
WIPO sectorElectrical engineering

Abstract

A method of operating a device comprising: a first conductor layer defining a plurality of source conductors each associated with a respective group of transistors, and a plurality of drain conductors each associated with a respective transistor; a semiconductor layer defining semiconductor channels between said source and drain conductors; a second conductor layer defining a plurality of gate conductors each associated with a respective set of transistors, and one or more storage capacitor conductors capacitively coupled to the drain conductors for a respective set of transistors; the method comprising: using the gate conductors to switch the transistors between on and off states; and using the storage capacitor conductors to reduce the conductivity of one or more semiconductor layer connecting the drain conductor of each transistor in the on state to source and/or drain conductors other than those associated with that transistor.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.