Array substrate and method of manufacturing the same
US9837477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2015 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Sep 25, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide an array substrate and a method of manufacturing the same. The method comprises: forming a gate electrode pattern, a gate insulation layer, an active layer pattern and an etching stopping layer on a substrate; forming a photoresist layer on the etching stopping layer; performing a single patterning process on the photoresist layer, such that photoresist in the first region is partially etched off, photoresist in the second region is completely etched off, and photoresist in the third region is completely remained; and performing a single etching process, such that residual photoresist in the first region and a portion of the etching stopping layer in the first region are etched off, and at the same time, a portion of the etching stopping layer and a portion of the gate insulation layer in the second region are etched off.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.