Dynamically adjustable decimation filter circuitry
US9837988B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2015 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Sep 16, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0664
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Decimation filter circuitry may include polyphase filtering structures that perform decimation filtering using filter coefficients. Generic polyphase filtering structures do not take advantage of symmetries between the corresponding filter coefficients. If desired, the arrangement of the polyphase filtering structures in the decimation filter circuitry may be optimized relative to generic polyphase filtering structures to take advantage of corresponding filter coefficient symmetries, thereby allowing for implementation of dynamic decimation ratios and a dynamic number of channels while reducing the number of required multipliers by half with respect to generic polyphase filters. Decimation filters may include pre-adder circuitry that receives first and second portions of a data stream and adds corresponding samples from the first and second portions to generate pre-added values. Convolving circuitry may generate filtered output data by convolving the pre-added values with corresponding filter coefficients based on symmetry of the filter coefficients.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.