Integrated circuit chip and its impedance calibration method
US9838011B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Aug 12, 2034 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip includes at least one driver circuit of single-ended structure and the first drive circuit, the first drive circuit and the at least one driver circuit of single-ended structure have the same structure, the first drive circuit includes a plurality of parallel-connected PMOS tubes and a plurality of parallel-connected NMOS tubes, the plurality of parallel-connected PMOS tubes connect the plurality of parallel-connected NMOS tube in series at a first node. After impedance calibration has been conducted, the chip confines a first impedance calibration code and a second impedance calibration code, and controls the at least one driver according to the first impedance calibration code and the second impedance calibration code; the first reference voltage is preferably configured to ¾ times of the supply voltage VDD, and the second reference voltage is preferably configured to ¼ times of the supply voltage VDD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.