Memory misalignment correction
US9838197B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2016 |
| Grant date | Dec 5, 2017 |
| Priority date | — |
| Expiry date | Apr 8, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A system and module for, and a method of correcting, memory misalignment in a phase shift keying receiver is disclosed. Embodiments include a system having: an analog front end for receiving a demodulated signal having a preamble portion, and for generating a digital register input signal including a received preamble portion; a finite state machine for selecting a memory address of the demodulated signal based on the received preamble portion; a preamble memory for storing all possible preambles contained within the demodulated signal and for supplying a selected preamble memory output corresponding to the selected memory address; and a memory alignment module configured to compare phase information of symbols of the preamble portion and preamble phase information of symbols of the selected preamble memory output. This system checks that the preamble portion of the register input signal aligns with the selected preamble memory output and makes corrections when necessary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.