Contact strap for memory array
US9842844B2 · kind B2 · utility
6Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 20, 2014 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Oct 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.