Array substrate and method of manufacturing the same, and display panel
US9842867B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 28, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Apr 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an array substrate and a method of manufacturing the same, and a display panel comprising the array substrate, for reducing a drop or height difference between surfaces of portions of a passivation layer located on either side of a source/drain electrode lead wire and a surface of a portion of passivation layer located on an upper surface of the source/drain electrode lead wire so as to increase an aperture ratio of the display panel. The method comprises: forming a source/drain electrode lead wire and a passivation layer successively on a base substrate, the passivation layer at least covering the source/drain electrode lead wire; and thinning a portion of the passivation layer located on the source/drain electrode lead wire such that a surface of the portion is higher than those of other portions of the passivation layer, at the time of patterning the passivation layer to form a via hole therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.