Multiple-input multiple-output wireless transceiver architecture
US9843378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2010 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Jul 12, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/0023
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A wireless transceiver contains a receiver and a transmitter. The receiver is operable in single-input single-output (SISO) mode as well as multiple-input multiple-output (MIMO) mode, and contains a pair of in-phase and quadrature signal processing chains and a baseband processor. In SISO mode, each of the processing chains in the pair is connected to receive a same modulated signal as input, and generates respective baseband outputs. The baseband processor processes the baseband outputs to demodulate the modulated signal. In MIMO mode, the signal processing chains in the pair receive different modulated signals and generate corresponding down-converted signals. The baseband processor processes the down-converted signals to demodulate the respective modulated signals received by the receiver. Corresponding techniques to provide MIMO in addition to SISO capabilities are implemented in the transmitter also. MIMO capability is thereby achieved in the wireless transceiver with minimal additional implementation area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.