Leakage mitigation at image storage node
US9843749B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2016 |
| Grant date | Dec 12, 2017 |
| Priority date | — |
| Expiry date | Feb 4, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/18
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A leakage mitigation circuit is provided. The leakage mitigation circuit includes an inverter coupled to a storage node, wherein the storage node receives a signal output by an imaging pixel having a first voltage level to be stored. The inverter inverts the signal to a second voltage level. A single transistor coupled to the inverter and the storage node inverts the signal output by the inverter to the first level to hold the signal at the storage node to its original level. A self-biased device coupled to the inverter lowers current disturbance related to the storage node and increase threshold voltage at which fluctuation of the level of the signal at the storage node causes the signal to be inverted by the inverter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.