Method and apparatus for asynchronous processor pipeline and bypass passing
US9846581B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2014 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Jan 1, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/3883
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.