Methods and devices for layered performance matching in memory systems using C-AMAT ratios
US9846646B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2016 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | Aug 17, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present disclosure describes a method of optimizing memory access in a hierarchical memory system. The method includes determining a request rate from an ith layer of the hierarchical memory system for each of n layers in the hierarchical memory system. The method also includes determining a supply rate from an (i+1)th layer of the hierarchical memory system for each of the n layers in the hierarchical memory system. The supply rate from the (i+1)th layer of the hierarchical memory system corresponds to the request rate from the ith layer of the hierarchical memory system. The method further includes adjusting a set of computer architecture parameters of the hierarchical memory system or a schedule associated with an instruction set to utilize heterogeneous computing resources within the hierarchical memory system to match a performance of each adjacent layer of the hierarchical memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.