Chip synchronization by a master-slave circuit
US9846665B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2014 |
| Grant date | Dec 19, 2017 |
| Priority date | — |
| Expiry date | May 25, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A master-slave circuit is disclosed that maintains synchronization between two integrated circuit chips, using minimal chip resources. In one embodiment, a single, bidirectional communication path is shared by the two chips. Meanwhile, only one I/O port on each chip is used to send and receive signals via the bidirectional communication path. The first chip to detect a signal event is designated the master and controls the bidirectional communication path. The master can communicate the status to the other chip by controlling the logic state of the I/O ports. When the second chip detects that the I/O port is controlled by the first chip, the second chip will logically deduce that it is now the slave. If both chips detect the signal event at substantially the same time, one of the two chips is pre-programmed to assume control of the I/O port as the master.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.